Article: SystemVerilog DPI (Direct Programming Interface) is an interface which can be used to interface SystemVerilog with foreign languages. These foreign languages can be C, C++, SystemC as well as others. DPIs consist of two layers: a SystemVerilog layer and a foreign language layer. Both the layers are isolated from each other.
Explanation
Direct Programming Interface (DPI) allows direct inter language function calls between the SystemVerilog and Foreign language. The functions implemented in Foreign language can be called from SystemVerilog and such functions are called Import functions. Similarly, functions implemented in SystemVerilog can be called from Foreign language (C/C++ or System C); such functions are called Export functions. DPIs allow transfer of data between two domains through function arguments and return.
Function import and export
1) Function Import:- A function implemented in Foreign language can be used in SystemVerilog by importing it. A Foreign language function used in SystemVerilog is called Imported function.
Properties of imported function and task
An Imported function shall complete their execution instantly and consume zero simulation time. Imported task can consume time.
Imported function can have input, output, and inout arguments.
The formal input arguments shall not be modified. If such arguments are changed within a function, the changes shall not be visible outside the function.
Imported function shall not assume any initial values of formal output arguments. The initial value of output arguments is undetermined and implementation dependent.
Imported function can access the initial value of a formal inout argument. Changes that the Imported function makes to a formal inout argument shall be visible outside the function.
An Imported function shall not free the memory allocated by SystemVerilog code nor expect SystemVerilog code to free memory allocated by Foreign code or (Foreign Compiler).
A call to an Imported task can result in suspension of the currently executing thread. This occurs when an Imported task calls an Exported task, and the Exported task executes a delay control, event control or wait statement. Thus it is possible for an Imported task to be simultaneously active in multiple execution threads.
An Imported function or task can be equip with special properties called pure or context.
Pure and context tasks and functions
Pure functions
A function whose results solely depends on the value of its input arguments with no side effects is called Pure function.
Properties of pure functions
Only Non-Void functions with no output or inout arguments can be called as Pure functions.
Functions specified as Pure shall have no side effects, their results need to depend solely on the values of their input arguments.
A Pure function call can be safely eliminated if its result is not needed or if its results for the same value of input arguments is available for reuse without needing to recalculate.
A Pure function is assumed not to directly or indirectly perform the following:
Perform any file operation.
Read or Write anything in Environment Variable, Shared memory, Sockets etc.
Access any persistent data like Global or Static variable.
An Imported task can never be declared Pure.
Context tasks and functions
An Imported task or function which calls "Exported" tasks or functions or accesses SystemVerilog data objects other than its actual arguments is called Context task or function.
Properties of context tasks and functions
1) A Context Imported task or function can access (read or write) any SystemVerilog data object by calling (PLI/VPI) or by calling Export task or function. Therefore, a call to Context task or function is a barrier for SystemVerilog compiler optimization.
Import declaration
import "DPI-C" function int calc_parity (input int a);
Export declaration
export "DPI-C" my_cfunction = function myfunction;
Calling Unix functions
SystemVerilog code can call Unix functions directly by importing them, with no need for a wrapper.
DPI example
Calling 'C' functions in SystemVerilog
C - code file
#include <stdio.h> #include <stdlib.h>
extern int add() {
int a = 10, b = 20;
a = a + b;
printf("Addition Successful and Result = %d\n", a);
return a; } SystemVerilog code file module tb_dpi;
import "DPI-C" function int add();
import "DPI-C" function int sleep(input int secs);
int j; initial begin
$display("Entering in SystemVerilog Initial Block");
#20 j = add();
$display("Value of J = %d", j);
$display("Sleeping for 3 seconds with Unix function");
sleep(3);
$display("Exiting from SystemVerilog Initial Block");
#5 $finish; end endmodule References
SystemVerilog DPI Tutorial from Project VeriPage |
Source: IEEE.org IEEE Xplore Digital Library IEEE Standards IEEE Spectrum More Sites eTools Standards Access Standards Search Standards Standards Development Standards Adoption
Where Life Meets Standards
Products & Programs Alliance Management Services
Conformity Assessment & Certification
IEEE SA Open Source
Industry Affiliate Network (IAN)
Industry Connections
The National Electrical Safety Code® (NESC®)
Registration Authority
Government Engagement Program on Standards (GEPS)
Standards Fellowship
All Products & Programs
Focuses
Autonomous and Intelligent Systems (AIS)
Connectivity & Telecom Energy Foundational Technologies Government Engagement
Healthcare and Life Sciences
Mobility Get Involved
How to Get Involved
Events IEEE SA Membership Resources Training & Development News IEEE SA Newsletter Standards Store Beyond Standards Blog
Where Life Meets Standards
About Us MAC ADDRESS Superseded Standard IEEE 1800-2012
IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language
Purchase Access via Subscription Home Standards
IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language
The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing test benches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)
Sponsor Committee
C/DA - Design Automation
Learn More
About C/DA - Design Automation
Status Superseded Standard PAR Approval 2010-06-17 Superseded by 1800-2017 Superseding 1800-2009 Board Approval 2012-12-05 History ANSI Approved: 2014-10-23 Published: 2013-02-21 Working Group Details Society IEEE Computer Society Learn More
About IEEE Computer Society
Sponsor Committee
C/DA - Design Automation
Learn More
About C/DA - Design Automation
Working Group
1800_WG - SystemVerilog Language Working Group
IEEE Program Manager Vanessa Lalitte Contact Vanessa Lalitte Working Group Chair Tom Fitzpatrick
Other Activities From This Working Group
Active Projects Active Standards Superseded Standards Inactive-Withdrawn Standards Inactive-Reserved Standards
Current projects that have been authorized by the IEEE SA Standards
Board to develop a standard.
No Active Projects
Standards approved by the IEEE SA Standards Board that are within the
10-year lifecycle. 1800-2023
IEEE Approved Draft Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language
The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing test benches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.
Learn More About 1800-2023
These standards have been replaced with a revised version of the
standard, or by a compilation of the original active standard and all
its existing amendments, corrigenda, and errata.
1364-2001
IEEE Standard Verilog Hardware Description Language
Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
Learn More About 1364-2001 1800-2005
IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language
This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document. (Adopted as IEC 62530:2007)
Learn More About 1800-2005 1800-2017
IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language
The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages. (The PDF of this standard is available at no cost at https://ieeexplore.ieee.org/browse/standards/get-program/page compliments of Accellera Systems Initiative)
Learn More About 1800-2017 62530-2007
IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language
This standard provides a set of extensions to the IEEE 1364 Verilogu00ae hardware description language (HDL) to aid in the creation and verification of abstract architectural level models. It also includes design specification methods, embedded assertions language, testbench language including coverage and an assertions application programming interface (API), and a direct programming interface (DPI). This standard enables a productivity boost in design and validation and covers design, simulation, validation, and formal assertion-based verification flows.
Learn More About 62530-2007
These standards have been removed from active status through a ballot
where the standard is made inactive as a consensus decision of a
balloting group. No Inactive-Withdrawn Standards
These standards are removed from active status through an
administrative process for standards that have not undergone a revision
process within 10 years.
No Inactive-Reserved Standards LinkedIn Facebook Instagram YouTube X
Beyond Standards RSS Feed
IEEE SA About Us IEEE SA Membership Distributor Partner Program Training & Development Policies & Procedures Contact Us Board of Governors
About Board of Governors
Awards Committee
Entity Collaborative Activities Governance Board
Industry Connections Committee Registration Authority Committee Standards Board About Standards Board Board Approvals Audit Committee New Standards Committee Patent Committee Procedures Committee Standards Review Committee News & Events News IEEE SA Newsletter Events Beyond Standards Blog Home Sitemap Contact & Support Accessibility Nondiscrimination Policy IEEE Ethics Reporting IEEE Privacy Policy
IEEE SA Copyright Policy
© Copyright 2021
IEEE – All rights reserved. Use of this website signifies your agreement to the
IEEE Terms and Conditions
.
A not-for-profit organization, IEEE is the world’s largest technical professional organization dedicated to advancing technology for the benefit of humanity.
Subscribe
Subscribe to our Newsletter
Sign up for our monthly newsletter to learn about new developments, including resources, insights and more.
Thank you for signing up for the IEEE SA Newsletter. Check your email for a confirmation message. |